Sunday, August 23, 2009
Wednesday, August 12, 2009
The only virtual conference dedicated to the best in high performance computing. During this virtual event, you will have an opportunity to hear from compute and HPC guru Andy Bechtolsheim and leading industry analysts discussing the trends and issues facing the computational ecosystem. In addition, industry and technology exhibits provide virtual opportunities to discuss technologies, accomplishments, and collaborations in HPC, networking, storage, software, and data management software.
Date: Thursday, September 17, 2009
Time: 8:00 AM Pacific / 11:00 AM Eastern / 3:00 PM Greenwich Mean Time
And you can register here.
Wednesday, August 5, 2009
- You are running a HPC cluster in Amazon EC2 with SGE Service Domain Manager with Cloud Adapter
- The node simply crashed and you don't have a budget to replace it
- You may think of any scenario where you want remove a SGE execution host, but the execution host has gone down and is never going to come up.
But that's not the of the story. You can simply hammer SGE by cleaning the entries of such hosts by following method. Lets assume the host you want to remove is, HOST_GO_AWAY
- qconf -dattr hostgroup hostlist HOST_GO_AWAY@cloud_hosts >/dev/null
- qconf -dattr hostgroup hostlist HOST_GO_AWAY@allhosts >/dev/null
- qconf -dh HOST_GO_AWAY >/dev/null
- qconf -ds HOST_GO_AWAY >/dev/null
- qconf -de HOST_GO_AWAY >/dev/null
- rm -f /opt/sge/default/common/local_conf/HOST_GO_AWAY
Tuesday, August 4, 2009
I only wish if this app would have been open sourced then anyone could have built an proxy server within minutes. May be someone would do it someday. Let's hope so.
Sunday, August 2, 2009
February 28, 2006
Prof. Bob Brodersen
ABSTRACT: The ability of FPGA technology to exploit the advances in IC fabrication technology has resulted in the present situation in which a FPGA computing fabric is the most power and area efficient approach for general purpose parallel computing. This has occurred because the Von-Neumann processor architectures are now power limited and can no longer fully exploit the technology advances (thus the move to multi-cores). Hardware composed of arrays of FPGA's and memory has been design that achieves a TeraOp/second of performance per board with over an order of magnitude higher efficiency for the computation per unit power over conventional microprocessors.